1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same. More particularly, it relates to a semiconductor device allowing improvement in reliability of an insulating film (more specifically, a capacitor dielectric film of an MOS capacitor or a gate insulating film of an MOSFET) formed on a substrate, and to a method of manufacturing the same.
2. Description of the Background Art
FIG. 42 is a sectional view illustrating the structure of a first semiconductor device in the prior art. The prior-art first semiconductor device includes an SOI substrate 104, element isolation insulating films 105a through 105e, an NMOSFET 106a, a PMOSFET 106c, and MOS capacitors 106b and 106d. The MOS capacitors 106b and 106d are usable as decoupling capacitors, for example. The SOI substrate 104 includes a silicon substrate 101, a BOX (buried oxide) layer 102, and a P-type silicon layer 103 stacked in this order. The element isolation insulating films 105a through 105e are partially provided in the upper surface of the silicon layer 103. Bottom surfaces of the element isolation insulating films 105a through 105e have no contact with the upper surface of the BOX layer 102. The element isolation insulating film arranged in this manner is called as xe2x80x9can element isolation insulating film of partial isolation typexe2x80x9d.
The NMOSFET 106a includes a gate oxide film 107a provided on the upper surface of the silicon layer 103, a gate electrode 108a, and a pair of N+-type source/drain regions 109a. The MOS capacitor 106b includes a capacitor dielectric film 107b provided on the upper surface of the silicon layer 103, a capacitor upper electrode 108b, and a pair of P+-type contact regions 109b. The PMOSFET 106c includes a gate oxide film 107c provided on the upper surface of the silicon layer 103, a gate electrode 108c, and a pair of P+-type source/drain regions 109c. The MOS capacitor 106d includes a capacitor dielectric film 107d provided on the upper surface of the silicon layer 103, a capacitor upper electrode 108d, and a pair of N+-type contact regions 109d. 
By ion implantation process, a P-type impurity or N-type impurity for element isolation is implanted at an impurity concentration P1 or N1 into the silicon layer 103 defined between each bottom surface of the element isolation insulating films 105a through 105e and the upper surface of the BOX layer 102. Resulting from this implantation, a P-type impurity or N-type impurity is implanted at an impurity concentration P2 or N2 into the silicon layer 103 defined under the gate oxide films 107a, 107c and the capacitor dielectric films 107b, 107d, and in the vicinity of an interface between the silicon layer 103 and the BOX layer 102.
By ion implantation process, a P-type impurity or N-type impurity for controlling threshold voltage of the NMOSFET 106a or PMOSFET 106c is further implanted at an impurity concentration P3 or N3 into the upper surface of the silicon layer 103 defined under the gate oxide films 107a and 107c. Resulting from this implantation, a P-type impurity or N-type impurity is implanted at an impurity concentration of P3 or N3 into the upper surface of the silicon layer 103 defined under the capacitor dielectric films 107b and 107d. 
FIG. 43 is a sectional view illustrating the structure of a second semiconductor device in the prior art. The prior-art second semiconductor device includes a P-type silicon substrate 110 having an impurity concentration P0, a P-type well 111 having an impurity concentration P2, an N-type well 112 having an impurity concentration N2, the element isolation insulating films 105a through 105e, the NMOSFET 106a, the PMOSFET 106c, and the MOS capacitors 106b and 106d. The P-type well 111 and the N-type well 112 are provided in the upper surface of the silicon substrate 110. The MOS capacitor 106b is provided on the P-type well 111, and the MOS capacitor 106d is provided on the N-type well 112.
As seen from the foregoing, in the first and second semiconductor devices of the prior art, the silicon layer 103 or the silicon substrate 110 bears the same impurity profile under the gate oxide film 107a and under the capacitor dielectric film 107b. Further, the silicon layer 103 or the silicon substrate 110 bears the same impurity profile under the gate oxide film 107c and under the capacitor dielectric film 107d. 
As a semiconductor integrated circuit increases in scale, the effective time period for applying voltage to the capacitor upper electrodes 108b and 108d may be longer than that for the gate electrodes 108a and 108c. As a result, the capacitor dielectric films 107b and 107d are required to be more reliable than the gate oxide films 107a and 107c. More specifically, when the MOS capacitors 106b and 106d are used as decoupling capacitors, the capacitor upper electrodes 108b and 108d receive DC voltage continuously applied thereto, requiring higher reliability of the capacitor dielectric films 107b and 107d. 
Such requirement for reliability is not limited to the MOS capacitor. That is, in an MOSFET receiving high voltage applied to a gate electrode thereof, a gate insulating film is also required to have high reliability. Hence, comparing the MOSFETs in voltage level, the one receiving higher gate voltage should be improved more for increasing reliability of a gate insulating film thereof than another receiving lower gate voltage.
However, improvement for increasing reliability cannot be found in the prior-art first and second semiconductor devices. These first and second semiconductor devices each experience the problem of insufficient reliability of the capacitor dielectric films 107b and 107d. 
It is therefore an object of the present invention to provide a semiconductor device and a method of manufacturing the same allowing improvement in reliability of an insulating film provided on a main surface of a substrate (a capacitor dielectric film of an MOS capacitor or a gate insulating film of an MOSFET).
According to a first aspect of the present invention, the semiconductor device includes an SOI substrate, a first MOSFET, a first impurity-injected region of a predetermined conductivity type, and a first MOS capacitor. The SOI substrate includes a support substrate, an insulating layer, and a semiconductor layer having a first concentration of the predetermined conductivity type stacked in this order. The first MOSFET is provided in a first element forming region of the SOI substrate, and includes a first gate insulating film provided on a main surface of the semiconductor layer. The first impurity-injected region is provided under the first gate insulating film, extending in the semiconductor layer from a certain depth from the main surface to a depth greater than the certain depth. The first MOS capacitor is provided in a second element forming region of the SOI substrate, and includes a first capacitor dielectric film provided on the main surface. The first impurity-injected region has a first impurity concentration distribution given by a second concentration higher than the first concentration. The semiconductor layer has a second impurity concentration distribution given by the first concentration under the first capacitor dielectric film. The first concentration creating the second impurity concentration distribution uniformly extends in a depth direction from at least a certain depth from the main surface to a contact surface between the semiconductor layer and the insulating layer.
When the first concentration is the initial impurity concentration of the semiconductor layer, the method of manufacturing the semiconductor device includes the following step. In this step, a photoresist is provided to cover the second element forming region and an impurity is implanted by ion implantation process into the lower part of the semiconductor layer using the photoresist as a mask against implantation, to form the first impurity-injected region in the semiconductor layer in the first element forming region. Therefore, this ion implantation causes no damage to the semiconductor layer in the second element forming region. As a result, it is allowed to improve reliability of the first capacitor dielectric film to be formed later on the main surface of the semiconductor layer in the second element forming region.
According to a second aspect of the present invention, the semiconductor device includes a semiconductor substrate having a first concentration of a predetermined conductivity type, an MOSFET, an impurity-injected region of the predetermined conductivity type, and an MOS capacitor. The MOSFET is provided in a first element forming region of the semiconductor substrate, and includes a gate insulating film provided on a first main surface of the semiconductor substrate. The impurity-injected region is provided under the gate insulating film, extending in the first main surface. The MOS capacitor is provided in a second element forming region of the semiconductor substrate, and includes a capacitor dielectric film provided on the first main surface. The impurity-injected region has a first impurity concentration distribution given by a second concentration higher than the first concentration. The semiconductor substrate has a second impurity concentration distribution given by the first concentration under the capacitor dielectric film. The first concentration creating the second impurity concentration distribution uniformly and entirely extending in a depth direction from the first main surface to a second main surface opposite to the first main surface.
When the first concentration is the initial impurity concentration of the semiconductor substrate, the method of manufacturing the semiconductor device includes the following step. In this step, a photoresist is provided to cover the second element forming region and an impurity is implanted by ion implantation process into the first main surface of the semiconductor substrate using the photoresist as a mask against implantation, to form the impurity-injected region in the semiconductor substrate in the first element forming region. Therefore, this ion implantation causes no damage to the semiconductor substrate in the second element forming region. As a result, it is allowed to improve reliability of the capacitor dielectric film to be formed later on the first main surface of the semiconductor substrate in the second element forming region.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.